A divide-by-n counter is a logic block that produces one output
pulse for n input pulses. It can also be used as a scaler in which an
applied input frequency is reduced by a factor of n.
Counters form an extremely important group of TTL applications,
particularly in the areas of timing systems and digital instruments. For
instance, in a digital instrument called a frequency counter, we might
have six decades of decimal counters and associated decoder/drivers
powering a 6-digit display readout. The time base of the counter might
consist of a 1.0-MHz crystal oscillator and up to seven cascaded decade
dividers to get a precise measuring interval of 0.1, 1, or 10
seconds.
Digital clocks are basically counters. Some of these start with the
60-hertz power-line frequency and divide by 60 to get a l-pulse-persecond
output. This is in turn divided by 10, by 6, by 10, and by 6
again to get the minutes and hours information. If we like, we can continue
to add counters for AM/PM, day, and year indication.
A television servicing dot-and-bar generator might start with a 189-
kHz crystal oscillator, used for 12 vertical bars. This is divided by 6
to get a 31.500-kHz half-screen rate. Two divisions follow this-an
even divide-by-2 for the horizontal rate at 15,750 and an odd divideby-
525 to get the inferlaced vertical output of 60 hertz. By factoring
the divide-by-525 into a divide-by-15 and a divide-by-35, we can
obtain a 900-hertz intermediate frequency, useful to get 15 horizontal
lines.
Traditional counter design methods required you to start with gates
and JK flip-flops and work up to the desired count sequence. The
design process was lengthy and introduced problems such as glitches